The demand for smaller and more capable, portable electronic systems, combined with the increased level of integration in today's semiconductors, is driving a need for smaller semiconductor packages with greater numbers of input/output terminals. At the same time, there is relentless pressure to reduce the cost of all the components of consumer electronic systems. The quad flat no lead (“QFN”) semiconductor package family is among the smallest and most cost effective of all semiconductor packaging types, but when fabricated with conventional techniques and materials, has significant limitations. For instance, with QFN technology the number of I/O terminals and the electrical performance that the technology can support is limited.
QFN packages P (FIGS. 5-7) are conventionally assembled on an area array lead frame 1 (FIGS. 1 and 2) etched from a copper sheet. A lead frame 1 can contain from tens to thousands of package sites, each comprised of a die attach pad 2 (FIGS. 1, 2 and 5-7) surrounded by one or more rows of wire bond pads 4 (FIGS. 2 and 5-7). All of these package P components are attached to a common frame 1 by pieces of copper to maintain the position of the package P components relative to the rest of the lead frame 1 and to provide an electrical connection to all of the components, to facilitate plating of the bonding and soldering surfaces.
These connected structures, commonly known as tie bars 3 (FIGS. 1, 2 and 5-7) short all of the components of the lead frame 1 together. Therefore, these tie bars 3 must be designed such that they can all be disconnected from the common shorting structure 6 (FIGS. 1 and 2) surrounding each package P site during singulation of the individual packages P from the lead frame 1, leaving each die attach pad 2 and wire bond pad 4 electrically isolated. Typically, the design to facilitate severing the electrical connection of the tie bars 3 to the lead frame 1 involves connecting the tie bars 3 to the copper shorting structure 6 (FIGS. 1 and 2) surrounding each package P site, just outside of the final package P footprint. This shorting structure 6 is sawn away (along line X of FIG. 2) during the singulation process, leaving the tie bars 3 exposed at the edge of the package P.
The QFN lead frame 1 provides the parts of the package P that facilitate fixing the semiconductor die, such as an integrated circuit chip 7 (FIGS. 5-7) within the package P and the terminals that can be connected to the integrated circuit 7 through wire bonds 8 (FIGS. 5 and 6). The terminals, in the form of the wire bond pads 4, also provide a means of connecting to the electronic system board (such as a printed circuit board) through a solder joint 5 (FIGS. 5-7) on the surface opposite that of the wire bond 8 surface.
The requirement that all of the package P components be connected to the lead frame 1 by a metal structure, severely limits the number of leads that can be implemented in any given package P outline. For instance, wire bond pads 4 can be provided in multiple rows surrounding the die attach pads 2 with each row being a different distance away from the die attach pads 2. For any wire bond pads 4 inside the outermost row of wire bond pads 4, the tie bar 3 connecting structures must be routed between the pads 4 of the outer row, so that such tie bars 3 can extend to the common sorting structure 6 outboard of the package P isolation (along line X). The minimum scale of these tie bars 3 is such that only one can be routed between two adjacent pads 4. Thus, only two rows of pads 4 may be implemented in a standard QFN lead frame 1. Because of the current relationship between die size and lead count, standard QFN packages are limited to around one hundred terminals, with a majority of packages P having no more than about sixty terminals. This limitation rules out the use of QFN packaging by many types of dies that would otherwise benefit from the smaller size and lower cost of QFN technology.
While conventional QFN technology is very cost effective, there are still opportunities to further reduce the cost. After the integrated circuit chips 7 are attached and connected to the external lead wire bond pads 4 with wire bonds 8, the assembled lead frame 1 of multiple packages P is completely encapsulated with epoxy mold compound 9 (FIGS. 6 and 7), such as in a transfer molding process. Because the lead frame 1 is largely open front to back, a layer of high temperature tape T is applied to the back of the lead frame 1, prior to the assembly process, to define the back plane of each package P during molding. Because this tape T must withstand the high temperature bonding and the molding process, without adverse effect from the hot processes, the tape is relatively expensive. The process of applying the tape T, removing the tape T and removing adhesive residues, can add significant cost to processing each lead frame 1.
The most common method of singulation of the individual packages P from the lead frame 1 is by sawing (along line X of FIG. 2). Because the saw must remove all of the shorting structures 6 just outside the package P outline, in addition to cutting the epoxy mold compound 9, the process is substantially slower and blade life considerably shorter, as if only mold compound 9 is cut. Because the shorting structures 6 are not removed until the singulation process, this means that the dies cannot be tested until after singulation. Handling thousands of tiny packages P, and assuring each is presented to the tester in the correct orientation is much more expensive than being able to test the whole strip with each passage P in a known location.
A lead frame 1 based process, known as punch singulation, to some extent addresses the problem associated with saw singulation and allows testing in the lead frame 1 strip, but substantially increases cost by cutting utilization of the lead frame 1 to less than fifty percent of that of a saw singulated lead frame 1. Punch singulation also imposes a requirement for dedicated mold tooling for every basic lead frame design. Standard lead frames 1 designed for saw singulation use a single mold cap for all lead frames 1 of the same dimensions.
In both saw singulated and punch singulated packages P, the tie bars 3 are left in the completed packages P and represent both capacitive and inductive parasitic elements that cannot be removed. These now superfluous pieces of metal significantly impact the performance of the completed package P, precluding the use of QFN packages P for many high performance integrated circuit chips 7 and applications. Furthermore, the cost of this potentially rather valuable superfluous metal can be substantial and is wasted by the QFN process.
Several concepts have been advanced for QFN type substrates that eliminate the limitations of etched lead frames. Among those is a process that deposits the array of package components on a sacrificial carrier by electroplating. The carrier is first patterned with plating resist and the carrier, usually stainless steel, is slightly etched to enhance adhesion. The strip is then plated with gold and palladium to create an adhesion/barrier layer, then plated with Ni to around sixty microns thick. The top of the Ni bump is finished with a layer of electroplated Ag to facilitate wire bonding. After the strip is assembled and molded, the carrier strip is peeled away to leave a sheet of packaged dies that can be tested in the sheet and singulated at higher rates and yields than with conventional lead frames. This electroplated approach eliminates all of the issues associated with connective metal structures within the package and allows for very fine features. The plating process, however, results in strips that are very expensive compared to standard etched lead frames. This approach is described in U.S. Pat. No. 7,187,072 by Fukutomi, et al.
Another approach is a modification of the etched lead frame process wherein the front side pattern is etched to about half the thickness of the lead frame, and the backside of the lead frame strip is left intact, until after the molding process is complete. Once molding is complete, the backside pattern is printed and the lead frame etched to remove all of the metal except for the backside portion of the wire bond pads and die paddle. This double etch process eliminates all of the issues associated with connective metal structures within the package. The cost of the double etched lead frame is less than the electroplated version, but still more expensive than standard etched lead frames, and the etching and plating processes are environmentally undesirable.
One failure mode for a lead frame packaged integrated circuit is for the wire bond pads 4 to become disconnected from wire bonds 8 coupled thereto, especially when a shock load is experienced by the package (such as when an electronic device incorporating the package therein is dropped and hits a hard surface). The wire bond pad 4 can remain mounted to a printed circuit board or other electronic system board while separating slightly from surrounding epoxy mold compound, allowing the wire bond 8 to be severed from the wire bond pad 4. Accordingly, a further need exists for a lead carrier package which better holds the wire bond pads 4 within the entire package, especially when shock loads are experienced.
Another lead carrier known in the art and developed by Eoplex, Inc. of Redwood City, Calif. is known as a lead carrier with print-formed package components and is the subject of U.S. patent application Ser. No. 13/135,210, incorporated by reference herein in its entirety. This lead carrier with print-formed components is provided with an array of separate package sites in the form of a multi-package lead carrier (see for example FIGS. 3 and 4 for a general depiction of one form of this lead carrier). A sintered material, typically beginning as silver powder, is placed upon a temporary layer formed of high temperature resistant material, such as stainless steel. The stainless steel or other material forming the temporary layer supports the sintered material while it is heated to a sintering temperature.
The sintered material is located upon the temporary layer in separate structures preferably electrically isolated from each other (other than through the temporary layer) in the form of die attach pads and terminal pads. One or more terminal pads surround each die attach pad. Each die attach pad is configured to have an integrated circuit or other semiconductor device supported thereon. Wire bonds can be routed from the integrated circuit upon the die attach pad to the separate terminal pads surrounding each die attach pad (see for example FIG. 8). Mold compound can then be applied which encapsulates the die attach pads, integrated circuits, terminal pads and wire bonds (see for example FIGS. 9 and 10). Only surface mount joints defining under portions of the die attach pad and terminal pads remain unencapsulated (FIG. 10) because they are adjacent the temporary layer.
Once the mold compound of the lead carrier has hardened, the temporary layer can be peeled away from the remaining portions of the lead carrier, leaving a plurality of package sites with individual die attach pads and associated integrated circuits, terminal pads and wire bonds all embedded within a common mold compound. The individual package sites can then be cut from each other by cutting along boundaries between the package sites and surface mounted through the surface mount joints to an electronics system board or other support.
Because the package sites of the lead carrier and individual pads within the package sites are each electrically isolated from each other, other than through the temporary layer, these individual pads can be tested for electrical continuity while on the temporary layer. After removal of the temporary layer, but before singulation into separate packages, a variety of electrical performance characteristics can be tested. Furthermore, such packages could be tested after isolation from adjacent packages on the lead carrier utilizing known testing equipment utilized with QFN packages or other testing equipment.
Additionally, each pad of the lead carrier, including the die attach pads and the terminal pads, preferably has edges around peripheries thereof which are configured to mechanically engage with the mold compound somewhat. In particular, these edges can taper in an overhanging fashion, or be stepped in an overhanging fashion, or otherwise be configured so that at least a portion of each edge spaced from a bottom thereof extends further laterally than portions of each edge closer to a bottom portion of each edge. Thus, the mold compound, once hardened, locks the pads securely into the mold compound. In this way, the pads resist detachment from the wire bonds or otherwise becoming detached from the mold compound, especially when the temporary layer is peeled away, and keep the entire package as a single unitary package.